The packaging of integrated circuit (IC) chips is one step in the manufacturing process, contributing to their overall cost, performance and reliability. As semiconductor devices reach higher levels of integration, packaging of an IC chip accounts for a considerable portion of the cost of producing the device, and failure of the package leads to costly yield reduction.
Several packaging technologies are available. For example, wire bonding technology uses upward-facing chips with wires connected to each pad on the chip. In flip chip technology, a flip chip microelectronic assembly includes a direct electrical connection of a downward-facing (that is, “flipped”) chip onto a substrate, such as a printed circuit board (PCB) or a carrier using conductive pads of the chip.
Flip chips are typically made by placing solder balls on a silicon chip. Ball cracking is typically generated by strain caused by different coefficients of thermal expansion (CTE) between materials in the package assembly. For example, a silicon substrate of the chip typically has a CTE of higher than about 3 ppm/degree Celsius (° C.), a low-k dielectric of the chip typically has a CTE of higher than about 19 ppm/° C., while the package substrate typically has a CTE of higher than about 16 ppm/° C. The difference of CTEs introduces strain to the structure when a thermal change occurs.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to illustrate the relevant aspects of various embodiments and are not necessarily drawn to scale.